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1 general description the ds1683 is an integrated elapsed-time recorder con - taining a factory-calibrated, low-temperature-coefficient rc time base that eliminates the need for an external crystal. using eeprom technology to maintain data in the absence of power, the ds1683 requires no backup power source. the ds1683 detects and records the num - ber of falling edge transitions on the event pin as well as the total cumulative time that the event pin is held high. the alarm pin alerts the user when the total time accumulated equals or exceeds the user-programmed alarm value, or when the total number of events equals or exceeds the user-programmed alarm value. the polar - ity of the open-drain alarm pin can be programmed to either drive low or become high impedance upon an alarm condition. the ds1683 is ideal for applications that monitor the total amount of time that a device has been in operation and/or the number of uses since inception service, repair, or last calibration. applications high-temp, rugged, industrial applications where vibration or shock could damage a quartz crystal any system where time-of-use is important to track power-on-time recorder benefits and features s records the total time the event input has been active high and number of events (falling edges of event) that have occurred s 32-bit, nonvolatile, elapsed time counter (etc) monitors event duration with quarter seconds resolution and provides 34 years of total time accumulation s nonvolatile 16-bit event counter records the number of falling edges seen by the event pin s calibrated, low-temperature-coefficient rc time base s 16 bytes of user eeprom s password protection scheme (4 bytes) s i 2 c-compatible interface s +2.5v to +5.5v operating voltage range 19-6388; rev 0; 6/12 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maxim-ic.com/ds1683.related . ds1683 total-elapsed-time and event recorder with alarm for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com.
2 ds1683 total-elapsed-time and event recorder with alarm (all voltages referenced to gnd.) voltage range on v cc , alarm, sda, scl ........ -0.5v to +6.0v voltage range on event ........................ -0.5v to (v cc + 0.5v), not to exceed +6.0v continuous power dissipation (t a = +70 n c) so (derate 5.9mw/ n c above +70 n c) ....................... 470.6mw maximum junction temperature ..................................... +150 n c operating temperature range .......................... -40 n c to +85 n c programming temperature range ....................... 0 n c to +70 n c storage temperature range ............................ -55 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions (t a = -40 n c to +85 n c, unless otherwise noted.) dc electrical characteristics (v cc = 2.5v to 5.5v, t a = -40 n c to +85 n c, unless otherwise noted.) event timing (v cc = 2.5v to 5.5v, t a = -40 n c to +85 n c, unless otherwise noted.) parameter symbol conditions min typ max units supply voltage v cc (note 1) 2.5 5.5 v input logic 1 (scl, sda) v ih 0.7 x v cc v cc + 0.3 v input logic 0 (scl, sda) v il -0.3 0.3 x v cc v event input trip point v etp 0.3 x v cc 0.5 x v cc 0.7 x v cc v event trip point hysteresis v hys 1% of v cc power-on reset v por 2.4 v parameter symbol conditions min typ max units input leakage i li -1 +1 f a alarm output (i ol = 10ma) v ol 0.8 v sda output (i ol = 4ma) v ol 0.4 v active supply current i cca (note 1) 180 300 f a eeprom write current i ee (note 1) 250 350 f a parameter symbol conditions min typ max units time event minimum t g (note 1) 10 35 70 ms time event increment t ei (note 1) 237.5 250 262.5 ms time event max t em (note 2) 34 years clr alm to alarm set (note 2) 10 150 f s
3 ds1683 total-elapsed-time and event recorder with alarm note 1: all voltages are referenced to ground. currents entering the ic are specified as positive; currents exiting the ic are specifie d as negative. note 2: guaranteed by design. note 3: c b : total capacitance of one bus line in pf. note 4: eeprom write time begins after a stop condition occurs. note 5: a decoupling capacitor to supply high instantaneous currents during eeprom writes is recommended. a typical value is 0.01 f f. v cc must be maintained above v cc(min) , including transients, during eeprom writes. note 6: v cc must be at or above 2.5v for t w after the end of an event to ensure data transfer to the eeprom. note 7: memory locations to which this specification applies: user memory, etc alarm limit, event counter alarm limit, configuration, password value. note 8: memory locations to which this specification applies: event counter register, etc register. i 2 c ac electrical characteristics (v cc = 2.5v to 5.5v, t a = -40 n c to +85 n c, timing referenced to v il(max) and v ih(min) , unless otherwise noted.) ( figure 7 ) nonvolatile memory characteristics (v cc = 2.5v to 5.5v, unless otherwise noted.) parameter symbol conditions min typ max units scl clock frequency f scl 400 khz bus free time between stop and start conditions t buf 1.3 f s hold time (repeated) start condition t hd:sta 0.6 f s low period of scl t low 1.3 f s high period of scl t high 0.6 f s data hold time t hd:dat 0 0.9 f s data setup time t su:dat 100 ns start setup time t su:sta 0.6 f s sda and scl rise time t r (note 3) 20 + 0.1c b 300 ns sda and scl fall time t f (note 3) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 f s sda and scl capacitive loading c b (note 3) 400 pf eeprom write time t w (notes 4, 5, 6) 10 20 ms parameter symbol conditions min max units eeprom write cycles t a = +70 n c (note 7) 50,000 writes eeprom write cycles (4 banks) t a = +70 n c (note 8) 200,000 writes
4 ds1683 total-elapsed-time and event recorder with alarm pin configuration pin description pin name function 1 event event input. the event pin controls when the values in the elapsed time counter (etc) register and the event counter register are incremented. the event pin also determines when the data in these registers is stored to eeprom. 2, 7 n.c. no connection. these pins are not connected internally. 3 alarm alarm output. the alarm pin is an open drain structure, and is set active when an alarm condition is met. the active state of this pin is controlled by the alrm pol bit located in the configuration register. once the alarm pin is active, it will remain active until the alarm condition is cleared and the clr alm bit in the command register is set. 4 gnd ground 5 scl i 2 c serial-clock input. the scl pin is the serial-clock input for the i 2 c synchronous communications channel. the scl pin is an input that requires an external pull-up resistor. 6 sda i 2 c serial-data input/output. the sda pin is the data input/output signal for the i 2 c synchronous com - munications channel. the sda pin is an open-drain i/o, which requires an external pullup resistor. 8 v cc +2.5v to +5.5v input supply event + n.c. alarm 1 2 3 4 8 7 6 5 gnd v cc n.c. sda scl so top view ds1683
5 ds1683 total-elapsed-time and event recorder with alarm detailed description the ds1683 is an elapsed-time recorder that tracks the accumulated time the event pin has been held high as well as the number of falling edge transitions seen by the event pin. the main application is to track the accumu - lated on-time and number of power cycles of a device or system. programmable alarm limits for both the accumu - lated on-time and number of falling edges of the event pin are available so that the user can be alerted when these conditions are met. the accumulated elapsed time that the event pin has been held high is stored in the 4-byte elapsed time counter (etc) register. the number of times the event pin sees a falling transition is stored in the 2-byte event counter register. the ds1683 includes password protection to prevent tampering with accumulated values, alarm limits, configuration settings, and user memory values. the etc, etc alarm limit, event counter, event counter alarm limit, configuration, password, and user memory values are stored in shadowed eeprom. on power-up, the values in the etc and event counter are loaded into sram locations. when the state of the event pin causes changes to the accumulated time and number of events, it is these sram registers that are incremented. block diagram elapsed time counter (etc) (registers 0ah?0dh) glitch filter event alarm sda scl alarm latch etc alarm enable etc alarm limit (registers 12h?15h) oscillator event alarm enable v cc v cc gnd i 2 c interface event alarm limit (registers 10h?11h) event counter (registers 08h?09h) status register (register 01h) configuration register (register 16h) user eeprom (registers 20h?2fh) command register (register 00h) password protection (registers 02h?05h) (registers 1ah?1dh) alarm polarity ds1683
6 ds1683 total-elapsed-time and event recorder with alarm when the contents of the etc and event counter registers match or exceed their programmable alarm limits, the alarm pin can be driven to its active state as set by the polarity bit, alrm pol, located in the configuration regis - ter. each of the alarm limits has an enable bit that should be used to determine whether or not the alarm pin should be activated when the alarm conditions are met. the ds1683 has an internal, low-temperature-coefficient, rc-based oscillator that is started on power-up. the ds1683 uses this rc time base to increment the etc register in 250ms increments while the event pin is held high. when the event pin is driven low, the etc register ceases to increment. event pin the ds1683 monitors the state of the event pin to determine when an event occurs. when the pin is pulled high, the etc and event counter values are transferred from shadowed eeprom to sram. while the event pin is held high, the value of the etc sram begins incre - menting once every 250ms. incrementing the etc sram value while event is high allows the device to increment the etc value without contributing to eeprom wear out. when the event pin falls to a logic 0, the event counter sram value increments by a value of one. also at this time the etc stops accumulating time. the values of the event and etc counter sram locations are then stored in the etc and event shadowed eeprom array. the event input is deglitched (t g ) to prevent short noise spikes from triggering an event. while the event pin is high, the i 2 c bus is unavailable for write commands, though read commands can still be executed. when the event pin transitions low, i 2 c com - munication is unavailable for t w (eeprom write time), after which i 2 c writes are possible. however, if an i 2 c write operation is underway, and the event pin transi - tions low to high, this operation is interrupted so that the etc and event counter registers can be updated. so it is important to terminate all i 2 c write transactions before transitioning the level on the event pin. an i 2 c read command can be performed regardless of the state of the event pin. on a low-to-high transition of the event pin, the i 2 c read command is allowed to complete. however, it is strongly recommended that all i 2 c communication be terminated before transitioning the level on the event pin. when the event pin is high and the device detects a start signal on the i 2 c bus, a snapshot of the data in the etc and event counter sram is made available on the i 2 c bus. when the event pin is low and the device detects a start signal on the i 2 c bus, data is transferred from the etc and event counter shadowed eeprom bank memory. elapsed time counter (etc) register the elapsed time counter (etc) register is a 32-bit value that holds time in quarter-second resolution. the etc register consists of 4 bytes of memory in the memory map. once the counter reaches ffffffffh, counting stops. the etc register is backed by 4 banks of shad - owed eeprom, which allow for 200k+ write cycles to occur before a wearout condition. when an i 2 c read occurs while the event pin is high, a snapshot of the value from the etc sram is made available for the i 2 c bus. when the event pin is logic 0, i 2 c reads take data from the shadowed eeprom etc bank memory. on power-on reset (por), the etc value stored in the shadowed eeprom bank memory is loaded into the etc sram location ( figure 1 ). this also happens when a low- to-high transition occurs on the event pin, or when an i 2 c write to the etc register occurs. when data is written to the etc register, the value is stored in the shadowed eeprom bank memory and also in the corresponding etc sram location. this data is transferred after the stop of the i 2 c command. figure 1. data transfer between nonvolatile and volatile memory types 1 1 1 v cc event pin i 2 c write command to etc or event registers 1 shadowed eeprom is written to sram 2 sram is written to shadowed eeprom 2
7 ds1683 total-elapsed-time and event recorder with alarm on the falling edge of the event signal, the contents of the etc sram counter are written to the etc shadowed eeprom registers. when the event pin is low, the etc register can be written by the i 2 c bus. for example, when it comes time to reset the time stored in the etc register, an i 2 c write command can be issued to set all the bits to 0. etc alarm register the etc alarm register is a 32-bit value and contains the value that is compared to the accumulated etc value. when a nonzero value is programmed into the etc alarm register, the etc alarm function is enabled and the ds1683 compares the value in the etc sram counter with the programmed value in the etc alarm register. when the etc sram counter matches or exceeds the alarm value, the etc alarm flag (etc af) is set. note: to disable the etc alarm function, program the etc alarm register to a value of all 0s. an alarm value of all 0s disables the etc alarm function. event counter register this 16-bit event counter stores the number of falling edges seen on the event pin. once the event counter reaches a value of ffffh, event counting stops. the event counter register is backed by four banks of shad - owed eeprom, which allow for 200k+ write cycles occur before a wearout condition. when an i 2 c read occurs when the event pin is high, a snapshot of the value from the event counter sram is made available for the i 2 c bus. when the event pin is logic 0, i 2 c reads take data from the shadowed eeprom event counter bank memory. on por, the event counter value stored in shadowed eeprom bank memory is loaded into the event counter sram location. this also happens when a low-to-high transition occurs on the event pin, or when an i 2 c write to the event counter register occurs. when data is writ - ten to the event counter register, the value is stored in the shadowed eeprom bank memory, and also in the corresponding event counter sram location. this data is transferred after the stop of the i 2 c command. on the falling edge of the event signal, the event counter sram register is incremented by a value of one, and the contents of the event counter sram are written to the event counter shadowed eeprom. when the event pin is low, the event counter register can be written by the i 2 c bus. for example, when it comes time to reset the accumulated number of events in the event counter register, an i 2 c write command can be issued to set all of the bits to 0. event counter alarm register the event counter alarm register is a 16-bit register, and contains the value that is compared to the accumulated event counter value. when a nonzero value is programmed into the event counter alarm register, the event counter alarm function is enabled, and the ds1683 compares the value in the event counter sram with the programmed value in the event alarm register. when the event counter sram value matches or exceeds the alarm value, the event counter alarm flag (event af) is set. note: to disable the event counter alarm function, pro - gram the event counter alarm register to a value of all 0s. an alarm value of all 0s disables the event counter alarm function. alarm output the alarm pin is an open-drain structure, and set - ting the alarm polarity bit (alrm pol) located in the configuration register determines if the alarm output is active high or active low (default is active low). the ds1683 monitors the values in the etc and event counter registers and compares them to the values in the etc and event counter alarm registers. when the etc and event counter values match or exceed their corre - sponding alarm values, their alarm flags (event af and etc af, located in the status register) are set to a value of 1, indicating an alarm condition. if the correspond - ing enable bits (etc alrm en and event alrm en, located in the configuration register) are active, then the alarm output is driven to its active state and is latched. once the alarm condition has been cleared, the cor - responding alarm flag (event af and/or etc af) automatically clears. once the actual alarm condition is cleared, the clr alm bit must be used to clear an active alarm pin state. if the alarm condition is still present when the clr alm bit is toggled, the alarm simply reactivates and latches.
8 ds1683 total-elapsed-time and event recorder with alarm event logging when the ds1683 is powered up, the internal oscilla - tor starts; the etc and event counter values, which are recorded in the shadowed eeprom bank memory, are transferred to the etc and event counter sram loca - tions; and the device waits for an event (rising edge of the event signal). when an event triggers the input by transitioning the event pin from a low to a high level, the following occur: 1) the etc and event counter values are once again transferred from shadowed eeprom bank memory to their sram counter locations. 2) after the glitch filtering and t ei , the etc sram counter value increments. see figure 2 for timing. an event greater than time event minimum (t g ) but less than t ei (i.e., a low-high-low transition on event < t ei ) incre - ments the event counter sram value but not the etc sram value. 3) the etc sram value increments every t ei . the etc sram counter holds time in quarter-second resolution. 4) when the event pin goes low, the event counter sram value increments by one, the etc sram coun - ter stops incrementing, and the values from the etc and event counter sram locations are transferred to their shadowed eeprom counterparts. the i 2 c bus is not available for t w . the etc value does not roll over when ffffffffh, or approximately 34 years, is reached. the event counter value does not roll over when reaching a value of ffffh. while the event pin is high, i 2 c write commands are ignored, though i 2 c read commands are still possible. password protection from the factory, the ds1683 powers up without pass - word protection enabled. the intent is to provide a manufacturer an optional security feature to protect the configuration register, alarm registers, user eeprom, etc and event counter settings, and the password value (pwv). the customer is not able to alter the configuration register, alarm registers, etc or event counter, user eeprom or password value settings if the password conditions are not met. the ds1683 password is stored in the 4-byte read- only password value register, located at 1ahC1dh. the default value for this register is ffffffffh. to change this value, a 4-byte i 2 c write command must be issued. the 4 bytes of the new password must be issued with the same i 2 c write command. once the stop of the i 2 c write command is issued, the password value register is updated with the new 4-byte value. the password entry bytes (pwe) are where the user enters the 4-byte password to unlock access to the DS1683S eeprom locations. when writing the pwe value, the user must issue a 4-byte i 2 c write command starting at location 02h. this 4-byte value must match the 4-byte password value stored in registers 1ahC1dh. figure 2. event input timing internal event clock t g t ei event inpu t
9 ds1683 total-elapsed-time and event recorder with alarm if the password value has been changed from the factory default setting, the user has to enter this new password value into the pwe registers after a power cycle in order to unlock the memory again. see figure 3 for examples of writing the 4-byte password value and the 4-byte password entry value. user memory the ds1683 has 16 bytes of user-programmable, eeprom memory. user memory is set to read-only if the correct password is not entered into the password entry bytes. if the correct password is entered into the password entry bytes, the data can be written to the user memory and stored in eeprom with the correct i 2 c write command. figure 3. password value and password entry i 2 c examples communications key s notes p sr a n start 8-bit address or data repeated start stop ack not ack white boxes indicate the master is controlling sda shaded boxes indicate the slave is controlling sda write the 4-byte password value (registers 1ah through 1dh) with a single transaction to slave address d6h write the 4-byte password entry (registers 02h through 05h) with a single transaction to slave address d6h xxxxxxxx s 1101 10 aa byte 1 a byte 4 ap 1) all bytes are sent most significant bit first . 2) the first byte sent after a start condition is always the slave address followed by the read/write bit. 1 00 0011 0 0 1 byte 2 a s 1101 10 aa byte 1 a 1 00 0001 0 0 0 byte 2 a byte 3 a byte 4 ap byte 3 a
10 ds1683 total-elapsed-time and event recorder with alarm table 1. register memory map note: i 2 c reads from memory locations that do not exist report a value of ffh. v: volatile (sram); nv: nonvolatile (eeprom). * the pwe and pwv bytes read back 0s. address read/write name volatile/ nonvolatile factory default/power- up default password protection function 00h read/write command v 00h no command register 01h read status v 00h no status register 02hC05h read*/write pwe v ffh no password entry registers 06hC07h rsvd reserved 08hC09h read/write event reg nv 00h yes event counter registers 0ahC0dh read/write etc reg nv 00h yes etc registers 0ehC0fh rsvd reserved 10hC11h read/write event counter alarm limit nv 00h yes event counter alarm limit registers 12hC15h read/write etc alarm limit nv 00h yes etc alarm limit registers 16h read/write config nv 00h yes configuration register 17hC19h rsvd reserved 1ahC1dh read*/write pwv nv ffh yes password value 1ehC1fh rsvd reserved 20hC2fh read/write user memory nv 00h yes user eeprom 30hCffh rsvd reserved
11 ds1683 total-elapsed-time and event recorder with alarm register 00h: command register register 01h: status register factory default/power-on value 00h read access all write access all memory type sram, volatile memory access n/a n/a n/a n/a n/a n/a n/a r/w 00h reserved reserved reserved reserved reserved reserved reserved clr alm bit 7 bit 0 7:1 reserved reserved 0 clr alm clear alarm bit. this bit reads as a 0. writing this bit to a 1 unlatches the active alarm output, set - ting the alarm pin to its inactive state if the alarm condition is no longer present. if the alarm condi - tion persists, the alarm pin once again asserts to its active state. factory default /power-on value 00h read access all write access n/a memory type sram, volatile memory access n/a n/a n/a r/w r/w r/w r/w r/w 01h reserved reserved reserved reserved reserved event event af etc af bit 7 bit 0 7:3 reserved reserved 2 event this bit indicates the status of the event pins logic level, detected after the t g glitch filter time. 1 event af default value = 0. if the value in the event counter sram value is greater than or equal to the event counter alarm limit value, then this bit is automatically set to a value of 1 to indicate an alarm event. when the event sram counter value is less than the event counter alarm limit, this bit automatically set to a value of 0, indicating that there is no event alarm. 0 etc af default value = 0. if the value in the etc sram value is greater than or equal to the etc alarm limit value, then this bit is automatically set to a value of 1 to indicate an alarm event. when the etc sram value is less than the etc alarm limit, this bit automatically set to a value of 0, indicating that there is no etc alarm.
12 ds1683 total-elapsed-time and event recorder with alarm registers 02hC05h: password entry (pwe) registers 08hC09h: event counter register factory default ff ff ff ffh read access n/a; reads as all 0s write access all memory type sram, volatile memory access r/w r/w r/w r/w r/w r/w r/w r/w 02h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 03h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 04h 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 05h 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 bit 7 bit 0 there is one 4-byte password for the ds1683. entering the correct password into the password entry (pwe) bytes allows write access to the event, etc, event counter alarm limit, etc alarm limit, configuration, password value, and user memory regis - ters. this value is write-only, and reads from this location result in all 0s. on power-up, the pwe bits are set to 1 to match the fac - tory default password value of all 1s. factory default 00 00h read access all write access pw memory type shadowed eeprom, nonvolatile memory access r/w r/w r/w r/w r/w r/w r/w r/w 08h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 09h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 bit 7 bit 0 the event counter register is a shadowed eeprom register that contains the number of times a falling edge of the event pin has occurred. on power-up, on every rising edge of the event pin, and after an i 2 c write to the event counter register, the value from the shadowed eeprom is loaded up into the event counter memory (sram). it is this memory that is incremented on the falling edge of the event pin. on the falling edge of the event pin, this value in sram memory is then written to the shadowed eeprom memory to store the number of times there has been a falling edge on the event pin.
13 ds1683 total-elapsed-time and event recorder with alarm registers 0ahC0dh: etc register registers 10hC11h: event counter alarm limit register factory default 00 00 00 00h read access all write access pw memory type shadowed eeprom, nonvolatile memory access r/w r/w r/w r/w r/w r/w r/w r/w 0ah 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 0bh 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 0ch 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 0dh 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 bit 7 bit 0 the etc register is a shadowed eeprom register that contains the accumulated time in 250ms increments that the event pin has been held high. on power-up, on every rising edge of the event pin, and after an i 2 c write to the etc register, the value from the shadowed eeprom location is loaded into the etc counter memory (sram). when the event pin is high, it is this sram memory that is incremented once every 250ms. on the falling edge of the event pin, this value in sram memory is then written to the shadowed eeprom memory to store the accumulated time in 250ms increments. factory default 00 00h read access all write access pw memory type shadowed eeprom, nonvolatile memory access r/w r/w r/w r/w r/w r/w r/w r/w 10h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 11h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 bit 7 bit 0 the event counter alarm limit is a shadowed eeprom register, and when the event counter register value equals or exceeds the event counter alarm limit value, the event flag bit (event af bit, register 01h, bit 1) goes active high. when the event counter register value drops below the event counter alarm limit value, the event af bit automatically clears.
14 ds1683 total-elapsed-time and event recorder with alarm registers 12hC15h: etc alarm limit register register 16h: configuration register factory default 00 00 00 00h read access all write access pw memory type shadowed eeprom, nonvolatile memory access r/w r/w r/w r/w r/w r/w r/w r/w 12h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 13h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 14h 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 15h 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 bit 7 bit 0 the etc alarm limit is a shadowed eeprom, and when the etc register value equals or exceeds the etc alarm limit value, the etc flag bit (etc af bit, register 01h, bit 0) goes active high. when the etc register value drops below the etc alarm limit value, the event af bit automatically clears. factory default /power-on value 00h read access all write access pw memory type shadowed eeprom, nonvolatile memory access n/a n/a n/a r/w r/w r/w r/w r/w 01h reserved reserved reserved reserved reserved etc alrm en event alrm en alrm pol bit 7 bit 0 7:3 reserved reserved 2 etc alrm en default value = 0, which is disabled. when set to a 1, and if the etc register is equal to or greater than the etc alarm limit, then this device triggers the etc alarm flag (etc af), and the alarm pin goes to its active state. 1 event alrm en default value = 0, which is disabled. when set to a 1, and if the event counter register is equal to or greater than the event counter alarm limit, then this device triggers the event counter alarm flag (event af), and the alarm pin goes to its active state. 0 alrm pol default value = 0, which sets the alarm output active low. when set to a 1, the alarm output is active high.
15 ds1683 total-elapsed-time and event recorder with alarm registers 1ahC1dh: password value (pwv) registers 20hC2fh: user memory factory default ff ff ff ffh read access n/a; reads as all 0s write access pw memory type shadowed eeprom, nonvolatile memory access r/w r/w r/w r/w r/w r/w r/w r/w 1ah 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1bh 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 1ch 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 1dh 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 bit 7 bit 0 the default value for the four password value (pwv) is all 1s (ff ff ff ffh). the intent is to provide a manufacturer with a security feature to protect the configuration register, alarm registers, user eeprom, etc and event counter registers, and the password setting (pwv). the customer is not able to alter the configuration register, alarm registers, user eeprom, etc or event counter registers, or password setting if the password conditions are not met. factory default 00h for all locations read access all write access pw memory type eeprom, nonvolatile there are 16 bytes of user-programmable eeprom memory. user memory is set to read-only if the correct password is not entered into the password entry bytes. if the correct password is entered into the password entry bytes, the data can be written to the user memory and stored in eeprom with the correct i 2 c write command. the user memory locations can be read regard - less of the password protection.
16 ds1683 total-elapsed-time and event recorder with alarm sample applications figure 4 shows the ds1683 measuring total run time and operating from a battery with the alarm pin connected to an led. when the trigger switch is closed, the event pin is pulled high and the etc register begins increment - ing. when the trigger switch is opened, the event pin is pulled low by the resistor, the etc register stops incre - menting, the event counter register is incremented by one, and the values of both the etc and event counter are stored in shadowed eeprom. when the etc or event counter alarm conditions are met, the alarm pin pulls active low (the factory default setting), and current flows through the led, indicating an alarm condition. figure 5 shows the ds1683 in a total time-of-use applica - tion where power may be removed at the same time as the end of the event. the v cc slew rate at power-down is fast with respect to t w . a capacitor maintains v cc on the ds1683 above 2.5v until the eeprom write completes. a schottky diode blocks current from the capacitor to other devices connected to v cc . the v cc holding capacitor value of 30 f f is calculated using the maximum eeprom write current and eeprom write time. this assumes that the v cc slew rate allows time from event trip point to v cc at 2.5v on the ds1683 is at least t w. figure 6 shows the ds1683 in a total time-of-use applica - tion with power that can be removed at the same time as the end of the event. in this application, the v cc slew rate at power-down is slow with respect to t w . the external rst ic ends the event as v cc begins to drop. v cc must remain above 2.5v until the end of t w . both circuits in figure 5 and figure 6 are read-only because the state of the event pin is tied v cc . because the event pin is a logic 1 while v cc is applied, i 2 c write commands are disabled, thus only i 2 c read commands are possible in these configurations. figure 4. total run time figure 5. total time-of-use application with fast v cc slew rate (read-only) figure 6. total time-of-use application with slow v cc slew rate (read-only) ds1683 v cc event trigger switch led scl alarm sda gnd 0.01f ds1683 v cc event led scl alarm sda gnd 0.01f 30f v cc ds1683 v cc alarm led scl event sda gnd 0.01f v cc v cc reset ic
17 ds1683 total-elapsed-time and event recorder with alarm i 2 c serial interface description i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. see figure 7 and the i 2 c ac electrical characteristics table for additional information. master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses and start and stop conditions. slave devices: slave devices send and receive data at the masters request. bus idle or not busy: time between stop and start conditions when both sda and scl are inac - tive and in their logic-high states. depending on the device, when the bus is idle it initiates a low-power mode for slave devices. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. repeated start condition: the master can use a repeated start condition at the end of one data trans - fer to indicate that it will immediately initiate a new data transfer following the current one. repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identically to a normal start condition. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold time requirements. data is shifted into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of setup time before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock pulses including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowl - edgement (ack) or not-acknowledge (nack) is always the 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a zero during the 9th bit. a device performs a nack by transmitting a one (done by releasing sda) during the 9th bit. timing ( figure 7 ) for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is properly receiving figure 7. i 2 c timing diagram scl note: timing is referenced to v il(max) and v ih(min) . sda stop start repeated start t buf t hd:sta t hd:dat t su:dat t su:sto t hd:sta t sp t su:sta t high t r t f t low
18 ds1683 total-elapsed-time and event recorder with alarm data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to terminate communication so the slave returns control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave address byte sent immediately following a start condition. the slave address byte contains the slave address in the most significant 7 bits and the r/ w bit in the least significant bit. the DS1683S slave address is d6h (1101 011r/ w , where r/ w is 0). when the r/ w bit is 0 (such as in d6h), the master is indicating it will write data to the slave. if r/ w is set to a 1 (d7h in this case), the master is indicat - ing it wants to read from the slave. see figure 8 . if an incorrect (nonmatching) slave address is written, the ds1683 assumes the master is communicating with another i 2 c device and ignores the communication until the next start condition is sent. memory address: during an i 2 c write operation to the ds1683, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the sec - ond byte transmitted during a write operation following the slave address byte. i 2 c communication writing a single byte to a slave: the master must generate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and generate a stop condition. the mas - ter must read the slaves acknowledgement during all byte write operations. when writing to the ds1683, eeprom is written fol - lowing the stop condition at the end of the write command. to change the setting without changing the eeprom, terminate the write with a repeated start condition before the next stop condition occurs. using a repeated start condition prevents the t w delay required for the eeprom write cycle to finish. for a write command, data is transferred after receiv - ing a stop. writing multiple bytes to a slave: to write multiple bytes to a slave, the master generates a start condi - tion, writes the slave address byte (r/ w = 0), writes the memory address, writes up to 8 data bytes, and gener - ates a stop condition. the ds1683 writes 1 to 8 bytes (one page or row) with a single write transaction. this is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. the address counter limits the write to one 8-byte page (one row of the memory map). attempts to write to additional pages of memory without sending a stop condition between pages result in the address counter wrapping around to the beginning of the pres - ent row. for example, a 3-byte write starts at address 06h and writes 3 data bytes (11h, 22h, and 33h) to three consecutive addresses. the result is that addresses 06h and 07h would contain 11h and 22h, respectively, and the third data byte, 33h, would be written to address 00h. to prevent address wrapping from occurring, the master must send a stop condi - tion at the end of the page, then wait for the bus-free or eeprom write time to elapse. then the master can generate a new start condition and write the slave address byte (r/ w = 0) and the first memory address of the next memory row before continuing to write data. acknowledge polling: any time a eeprom byte is written, the ds1683 requires the eeprom write time (t w ) after the stop condition to write the contents of the byte to eeprom. during the eeprom write time, the device does not acknowledge its slave address because it is busy. it is possible to take advantage figure 8. ds1683 i 2 c slave address 11 1 0r /w 1 1 0 msb lsb read/write bit slave address
19 ds1683 total-elapsed-time and event recorder with alarm of this phenomenon by repeatedly addressing the ds1683, which allows communication to continue as soon as the ds1683 is ready. the alternative to acknowledge polling is to wait for a maximum period of t w to elapse before attempting to access the device. eeprom write cycles: the DS1683S eeprom write cycles are specified in the nonvolatile memory characteristics table. the specification shown is at the worst-case temperature (hot). it can handle many additional writes at room temperature. reading a single byte from a slave: unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. to read a single byte from the slave, the master generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. however, since requiring the master to keep track of the memory address coun - ter is impractical, the following method should be used to perform reads from a specified memory location. manipulating the address counter for reads: a dummy write cycle can be used to force the address counter (or pointer) to a particular value. to do this, the master generates a start condition, writes the slave address byte (r/ w = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (r/ w = 1), reads data with ack or nack as applicable, and generates a stop condition. recall that the master must nack the last byte to inform the slave that no additional bytes will be read. see figure 9 for i 2 c com - munication examples. reading multiple bytes from a slave: the read operation can be used to read multiple bytes with a single transfer. when reading bytes from the slave, the master simply acks the data byte if it desires to read another byte before terminating the transaction. after the master reads the last byte it must nack to indicate the end of the transfer and generates a stop condition. applications information power-supply decoupling to achieve best results, it is recommended that the power supply is decoupled with a 0.01 f f or a 0.1 f f capacitor. use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the v cc and gnd pins to minimize lead inductance. sda and scl pullup resistors sda is an open-collector output on the ds1683 that requires a pullup resistor to realize high-logic levels. an i 2 c master using either an open-collector output with a pullup resistor or a push-pull output driver can be used for scl. pullup resistor values should be chosen to ensure that the rise and fall times listed in the i 2 c ac electrical characteristics are within specification.
20 ds1683 total-elapsed-time and event recorder with alarm figure 9. i 2 c examples +denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. ordering information part temp range pin-package DS1683S+ -40 n c to +85 n c 8 so DS1683S+t&r -40 n c to +85 n c 8 so package type package code outline no. land pattern no. 8 so s8+4 21-0041 90-0096 slave address start 1 1 0 1 0 1 1 r/ w slave ack msb lsb b7 b6 msb lsb register/memory address msb lsb data stop a) single byte write -write a value of 07h to the configuration register: register 16h b) single byte read -read the status register: register 01h c) two byte write -write a value of f0h 00h to the event counter alarm limit registers: registers 10h and 11h typical i 2 c write transaction start stop 11 01 01 10 0001000 0 10h start repeated start d7h master nack stop 11 01 01 10 00 0 00001 01h 11 01 0111 start 11 01 01 10 00010110 d6h d6h d6h 16h stop data f0h example i 2 c transactions 00 00 011 1 d) two byte read -read the two byte value of the event counter registers: registers 08h and 09h start stop 1 1010110 00 00 10 00 d6h 08h repeated start d7h master ack 11 01 01 11 data master nack data 00h 11 11 00 00 0 000 0000 07h read / write b5 b4 b3 b2 b1 b0 slave ack b7 b6 b5 b4 b3 b2 b1 b0 slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack slave ack
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated products, inc. 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 21 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 6/12 initial release ds1683 total-elapsed-time and event recorder with alarm

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